Data processing systems have generally been developed to provide system configurations which range from compact singleboard micro-computers to more complex high performance minicomputers. Such systems use microcode architecture in which macroinstructions are suitably decoded so as to provide access to a micro-instruction or to a sequence of more than one micro-instruction obtained from a suitable data store thereof.
In order to reduce the data storage space required for the microinstructions and to avoid handling a large number of "wide" instruction words, certain microcode systems have utilized multi-level, in most cases "two-level", microcode store techniques, as opposed to one-level microcode stores, as is known in the art. One such two-level microcode system which is used to increase the power of a conventional two-level microcode technique has been described in currently pending U.S. patent application Ser. No. 120,272, filed Feb. 11, 1980 and entitled "Data Processing System" as filed by Bernstein et al. and assigned to Data General Corporation of Westboro, Mass., such application being incorporated by reference herein.
In accordance with the system described therein, the microcontrol store is formed as an "orthogonal" store in which a first, or "vertical", microcontrol store provides a "narrow" microinstruction word portion having one field comprising a selected number of vertical microinstruction bits for selecting one of a plurality of second, or "horizontal", microinstructions from a second level, or horizontal, microcontrol store, one or more "modifier" fields, as described in such application, and a sequencing field for presenting the address of the next (i.e., each successive) vertical microinstruction in a sequence thereof. As described therein, vertical microinstructions (microcodes) can be fetched either from a CPU-resident vertical control ROM or from one or more external microcontrollers via one or more external microcontroller interface units. The external microcodes can be obtained at any one time from one of the plurality of external microcontroller units by the use of suitable time-multiplexing techniques using a time-multiplexed microcode bus.
While such system has provision for supplying external microcode information utilizing appropriate software, for example, the most effective way for providing such external microcode information is described with reference to the invention disclosed herein. Accordingly, in order to achieve effective use of both the CPU-resident microcode information and the external microcode information, the invention provides for suitable interface logic which permits the most effective control of the transfer of external microcode information from an external microcode unit. While the invention is applicable to such multi-level microcode systems, its use is not limited thereto and the principles thereof are also applicable to single-level systems.